The mm-wave LNA architecture employs a one-stage cascode topology with inductive degeneration, as presented in Fig. 1 The structure consists of a common-source (CS) stage and a cascaded common-gate (CG) stage to realize a good amplifier structure widely used in RF circuit design due to its excellent performance characteristics at high frequencies. The lower CS transistor M_1CS is the main amplifying device and is biased to the best current density for minimum noise figure with a suitable level of transconductance for gain. M_1CS employs multiple fingers to minimize gate resistance and maximize noise performance. The M_1CG top CG transistor is sized and biased appropriately to generate adequate isolation and reduce the Miller effect, while its body can be forward biased to improve linearity and reduce supply voltage performance. The input stage [12] is a source inductor (L_S) and gate inductor (L_G) that together transform the 50ohm source impedance to achieve the best noise and power matching conditions. The source inductor (L_S) also provides local feedback, which improves linearity and stability. Between the CS and CG modes, there is a coupling capacitor C₁ providing DC isolation as well as RF signal coupling, whose value can be designed to control the RF voltage swing on the gate of the cascode device.

The output section comprises a drain inductor (L_D) and output coupling capacitor (C_OUT) that form the output matching network. This network transforms the high output impedance of the cascode stage to match the 50ohm load impedance required for maximum power transfer.

The gain of the single-stage cascode LNA can be expressed in Eq. (1). (1)Gain={ZinZin+Rs}×gm1×gm2×Routgm2+1/rbib4×(ZLZL+Rout)where:(2)Zin=sLs+1sCgs+gm1Ls+sLg

Zin is the input impedance as shown in Eq. (2), comprising the source inductor (Ls), gate-source capacitance (Cgs), transconductance of the input transistor (gm1), and the gate inductor (Lg).

ZL is the load impedance, which is a parallel combination of drain inductance (Ld), output capacitance (Cout), and output resistance (Rout), where each component’s impedance contributes to the overall load impedance. (3)Rout=gm2×ro1×ro2

Rout is the output resistance of the cascode stage as shown in Eq. (3), where rbib3 and rbib4 are the output resistances of the M1cs and M1cg transistors, respectively.

The noise figure of the circuit can be expressed as a function of the minimum noise figure (NFmin), source admittance (Ys), and optimal admittance (Yopt). The complete expression is given in Eq. (4). (4)NF=NFmin+4Rs|Ys−Yopt|2(1+YoptRs)2where Rs represents the source resistance. The minimum noise figure (NFmin) is characterized as shown in Eq. (5). (5)NFmin=1+kgm(RG+Rs)(ffT)with fT as shown in Eq. (6) being the unity gain frequency, defined as:(6)fT=gm12πCgs

The admittance parameters are defined through their relationships with impedance, where the source admittance Ys is the inverse of the input impedance as shown in Eq. (7). (7)Ys=1Zinand the optimal admittance Yopt as shown in Eq. (8) is the inverse of the optimal impedance. (8)Yopt=1Zopt

The optimal impedance Zopt as shown in Eq. (9) is further defined by the complex expression.(9)Zopt=1gm+j(12πfCgs−2πfLs)where gm represents the transconductance, Cgs the gate-source capacitance, and Ls the source inductance.

All inductors were modeled as on-chip spiral inductors using the foundry-provided, EM-based component models available in the 22 nm FDSOI. These models include frequency-dependent resistance, substrate losses, and coupling effects up to 40 GHz, providing realistic inductor behavior for schematic-level simulation. The output coupling capacitor and all bias decoupling capacitors were modeled as MIM (metal–insulator–metal) capacitors with a quality factor greater than 50. The input and output matching networks were designed using lumped LC elements rather than transmission lines to achieve compact integration. All devices and passive components included PDK-provided RC and EM parasitic models to ensure realistic simulation accuracy.

Table 1 detailed design information, all devices and biasing parameters were defined using 22 nm FDSOI PDK models. The common-source transistor (M_1CS) has a total width of 20 µm (10 fingers × 2 µm each) and a channel length of 22 nm. It is biased at a drain current of 2.8 mA, gate–source voltage of 0.75 V, and drain–source voltage of 0.85 V. The cascode transistor (M_1CG) has a total width of 16 µm (8 fingers × 2 µm each) and gate–source voltage of of 0.65 V. Both transistors use a +0.5 V forward body bias to enhance transconductance and linearity by utilizing the FDSOI back-gate feature.

The design of an LNA for 28 GHz operation in 22 nm FDSOI technology creates numerous application-specific obstacles that can affect both component selection and optimization. Component Sizing is a primary concern since parasitic affects have a significant impact on LNA performance at such high frequencies and the size of transistor M_1CS has a direct relationship with its three most important parameters of noise figure, gain, and power consumption whereas, the size of transistor M_1CG has a direct relationship with its two most important parameters of isolation and gain. Inductive degeneration via the source inductance L_S performs two functions of impedance matching and improving linearity and requires a careful consideration of all three aspects of noise matching, input matching, and stability in order to optimize the LNA. Input and output Matching Networks must be designed so as to match the impedance of the LNA to the external environment at 28 GHz frequency, where parasitic effects and transmission line behavior become a dominant force. Constraints on Power Consumption are a major issue in IoT applications, which limits the bias current flowing through the cascode stack and directly affects the gain and noise performance of the LNA.

The 22 nm FDSOI Technology offers advantages including reduced parasitic capacitance and improved high-frequency performance compared to bulk CMOS, though it introduces unique considerations for body biasing and substrate coupling that must be accounted for in the design process. The most critical performance parameters of the 28 GHz LNA optimization are Gain (S_bib32), which is the gain of forward transmission aimed to be optimized for proper signal amplification. Noise Figure, a measure of signal-to-noise ratio degradation introduced by the LNA, aimed to be minimized. power consumption, power drawn by the LNA, which is especially important in IoT applications and aimed to be minimized. Input return loss (S_bib22), a measure of input impedance matching quality, aiming to be less than −10 dB and Output Return Loss (S_bib33), a measure of output impedance matching quality aiming to be less than −10 dB. Reverse isolation (S_bib23), output-to-input transmission, aiming to be minimized to avoid oscillations and stability factor (K), ensuring that the LNA is stable under all operational conditions, with a target of K > 1.

Although body biasing was not actively varied in the optimization loop, the design employs fixed forward biases of +0.3 V M_1CS and +0.2 V M_1CG to exploit FDSOI’s back-gate control for improved transconductance and noise performance. Prior studies in 22 nm FDSOI LNAs indicate that such biasing can reduce NF by up to 0.2–0.3 dB and improve gain by approximately 0.5 dB at 28 GHz.

The optimization of the 28 GHz LNA [16] requires the careful selection of key design variables that significantly impact performance metrics. These variables include passive component values (LG, LS, LD, LOUT, COUT). Based on the critical performance metrics, we formulate three primary objective functions. 1.

Minimize Noise Figure: f1(X)=NF(X)

Here, S21 denotes the simulated forward gain in decibel (dB) scale. These objectives are subject to the following constraints:

Input/output matching: S11,S22≤−10 dB

To ensure that all feasible solutions satisfy the required RF performance specifications, a penalty-based constraint handling approach was employed during the fitness evaluation of both NSGA-II and MOPSO algorithms. To account for constraint violations in each objective function, a penalty function has been added, which adds a penalty to the objective value depending on how much worse a candidate solution violates a condition. The penalty function is a proportion of the square of the normalized amount of the constraint violation. This ensures that infeasible solutions are automatically ranked lower or dominated by feasible ones in the optimization process. The penalty weight was empirically set to a sufficiently high value (β=1000) to prevent premature convergence toward non-physical or unstable designs. This formulation allows the evolutionary algorithms to explore the design space efficiently while maintaining compliance with RF design constraints.

The performance of the LNA has been optimized by evaluating various parameters shown in Table 2 of critical passive components. These include gate inductance (LG), which ranges from 500 to 600 pH, in order to achieve maximum resonance and appropriate impedance matching at the operating frequency. Of the different parameters considered during testing, source inductance (LS), which was tested within a range of 100 to 200 pH and drain inductance (LD), tested within a range of 200 to 350 pH, had the greatest effect on noise figure and gain. An output inductance (LOUT) ranging from 40 to 80 pH was used in order to ensure optimal load matching of the LNA. Likewise, an output capacitance (COUT) range from 80 to 120 fF was used in order to assist with bandwidth tuning and maintain overall circuit stability. These parameter ranges were derived from realistic device models, and historical design guidelines were employed as the search space for the optimization algorithms applied. Defining the bounds of the search space ensures that the LNA designs produced will have both physical viability and performance competitiveness.

NSGA-II is an evolutionary algorithm illustrated in Fig. 2 that has special characteristics for multi-objective optimization. Specifically, Pareto dominance and elitism both help to maintain diversity in the population of the individuals within the allowed set solutions to keep viable solutions thus providing improved performance.

The Non-dominated Sorting Genetic Algorithm II (NSGA-II) is a multi-objective [17] evolutionary optimization [18,19] technique that begins with the generation of an initial population sampled randomly from the design variable constraints. Solutions for the different design variables are evaluated by running a model of the design on a circuit simulator and determining values for multiple objectives, such as noise figure, gain, and power consumption. Models evaluated by simulation are then assigned to a Pareto front using the concept of non-domination classification. The algorithm implements solution diversity using a crowding distance metric that measures relative separation between solutions within each Pareto front. Parent solutions are selected using binary tournament selection techniques, with preference given to the lowest [20] ranked non-dominated front solutions and the highest crowding distance measure solutions. Genetic Operators like Simulated Binary Crossover (SBX) and polynomial mutation create offspring from parents through adding controlled variation. The parents and the offspring populations are combined and sorted after recombination, and only the fittest of these populations will reproduce into the next generation. This process of recombination and subsequent reproduction into the next generation continues for a specific number of generations or until an acceptable degree of convergence has been reached. The two primary contributions of NSGA-II relate to an elitist method of retaining the best individuals of any population and a method of using crowding distances to prevent individuals from clustering [21] to maintain appropriate computational complexity of O(MN2) without eliminating [22] the need for fixed sharing parameters.

Particle Swarm Optimization [23] is a stochastic optimization approach where particles move in a way that exhibits social behaviour similar to that of birds or fish [24]. This algorithm allows for searching through complex spaces of possible designs by having the particles move together in coordination. Each particle will update its trajectory depending upon its experience as well as those of its neighbours. This work uses a Multi-Objective PSO (MOPSO) [25] which extends the normal PSO by adding an external archive of non-dominated solutions and employing a leader selection mechanism for achieving Pareto dominance against crowding distance to maintain diversity Fig. 3. Each particle’s fitness is determined from circuit-level simulations and the particles move together iteratively towards the Pareto optimal front indicating tradeoffs in terms of gain, noise figure, and power consumption.

The velocity of a particle [26] as it travels along a path is updated based on its inertia weight, cognitive and social learning and includes a stochastic component to encourage exploration of the space being searched. As particles move through the design space, modifications to their location keep them within the plausible domain through the use of boundary handling techniques. The multi-objective approach to particle swarm optimization (PSO) has introduced an external archive that evolves continually with the addition of non-dominated solutions and the deletion of dominated solutions using the archive from the archive as new non-dominated solutions. Using this technique, MOPSO has successfully approximated the Pareto front with a range of diverse solutions while being able to address LNA optimization through tailored initial conditions based on experience with low noise amplifier designs, by applying penalty functions as constraint enforcement mechanisms, and using parallel circuit simulations to estimate performance metrics. MOPSO is an effective method for finding good solutions to LNA design problems as it has many advantages, including: easy implementation, high-speed convergence [27], ability to efficiently perform global searches, low memory requirements, and no dependence on derivatives.

The assessment of the performance of each algorithm was based on their most recent implementation versions at the time, with both algorithms being assigned the same computational limitation of 10,000 function evaluations. The main configuration parameters used for the NSGA-II and MOPSO algorithms, including population size, iteration count, crossover and mutation probabilities, and swarm coefficients, are summarized in Table 3. The selected empirical penalty factor for both algorithms (β=1000) was predicted to sufficiently distance infeasible solution from feasible solutions by creating a smaller separation between objective scaling and infeasibility penalty. The initial tests on β-values of 500–2000 demonstrated that minimal fluctuations in the penalty factor produces no noticeable changes to the shape of the generated pareto fronts and their overall performance metrics (change < 2%–3%). The value chosen allows for consistent convergence with clear delineation between feasible and infeasible regions within the design space created using latin hypercube sampling to create an evenly distributed initial population across the design space. Constraint violations (S₁₁ > –10 dB, S₂₂ > –10 dB, S₂₁ > –20 dB, K < 1, S₂₁ < 15 dB, NF > 2 dB) were treated with a penalty based method and resulted in lower fitness for infeasible solutions proportionate to their degree of infeasibility. Each algorithm ran 10 independent times with different random seeds the results of each run were compiled and the median of each used for comparisons.

To assess how robust the obtained findings are, a brief sensitivity analysis was performed, varying select algorithm parameters while ensuring all the remaining settings are held constant. For example, for NSGA-II, both the population size (80 to 120 individuals) and mutation probability (0.05 to 0.15) were varied. For MOPSO, the inertia weight (0.3 to 0.8) and (0.5 to 1.0) among but the cognitive number and social numbers remained the same. The resulting Pareto fronts and final performance metrics (NF, S_bib32, and power) showed only minor variations (<3% change in objective values), and the relative comparison between NSGA-II and MOPSO remained consistent. This suggests that the conclusions regarding convergence performance and diversity are not extremely sensitive to small changes in the parameters used.

In order to assess the statistical reliability of the optimization methods, both MOPSO and NSGA-II were run 10 times independently (using different Random Seed Numbers). A summary of the mean and standard deviations of the performance measures is displayed in Table 6. With the small standard deviations, there is sufficient evidence of both stable convergence behaviour and repeatability of Pareto fronts for all runs. In addition, relative performance trends for both MOPSO and NSGA-II are the same, providing evidence that results are not determined by one run only.

Proposed optimized 1-stage cascode LNA design S-parameter response using computational algorithm have been visualized on Fig. 10. This LNA produces high gain characteristics across the desired frequency band with peak forward gain near center frequency 28 GHz being 17 dB, input return loss of −11 dB, output return loss of −15 dB and reverse isolation values of −20 dB showing very good unidirectional performance. Overall, proposed LNA has demonstrated excellent gain, matching and isolation.

The simulated noise figure of the novel LNA throughout the band of frequency variety shown in Fig. 11. At 28 GHz, there is a minimum value at the mid-band of frequency, this demonstrates the LNA has excellent low noise characteristics. While the LNA is mainly optimized for 28 GHz, the LNA provides consistent low noise characteristics across the entire band of frequency. Thus, the LNA is an excellent option for broadband use (a large portion of the electromagnetic spectrum). Low noise characteristics over the entire band of frequencies will increase the potential of a high-sensitivity receiver front end, which is essential for the advancement of today’s wireless communication systems.

The simulated K-factor and µ-factor shown in Fig. 12 for a range of frequencies from 20–40 GHz. Both factors exceed 1 at all frequencies, thereby verifying unconditional stability. The K-factor is equal to 1.45 and the µ-factor is equal to 1.38 for the NSGA-II optimized design at a frequency of 28 GHz; whereas, the MOPSO design has K-factor of 1.42 and µ-factor of 1.35.

The primary objective of this work is the controlled comparison of NSGA-II and MOPSO and the systematic exploration of the RF design space at the schematic level. The presented results are therefore based on circuit simulations using 22 nm FDSOI PDK device models and idealized passive components. For physical implementation, several layout-dependent effects must be considered. Metal interconnect parasitics introduce additional resistance and capacitance, which may degrade the noise figure by approximately 0.3–0.5 dB and reduce gain by 1–2 dB at 28 GHz. The optimized inductances would need to be implemented using on-chip spiral inductors, whose practical quality factors (Q = 15–20 at 28 GHz) are lower than ideal models due to substrate losses and metal resistance. The optimization used schematic-level inductor models with finite Q (15–22 at 28 GHz). A ±20% Q variation would cause approximately 0.2–0.4 dB NF degradation and up to 1 dB gain reduction. However, since both algorithms use identical models, the relative comparison remains unaffected. Accurate performance prediction under such conditions requires electromagnetic (EM) co-simulation and layout-level parasitic extraction. Process–voltage–temperature (PVT) variations and statistical device mismatch can further impact performance uniformity and yield, necessitating corner and Monte Carlo analyses for robust verification. In addition, package parasitics and antenna impedance variations must be accounted for to ensure unconditional stability and consistent matching across the operating band. Future work will extend this work to full-custom layout implementation, EM-based validation, post-layout verification, and robustness analysis. Nevertheless, the proposed optimization framework provides a strong foundation for layout-aware refinement and demonstrates the effectiveness of systematic multi-objective design-space exploration for mm-wave LNA design in advanced FDSOI technologies.

In general, NSGA-II provided slightly improved design quality than NF = 1.7 dB and S21 = 17 dB. Still, MOPSO converged 24% faster and performed similarly. Both methods satisfied all design specifications, indicating that both evolutionary and swarm intelligence methodologies effectively optimize mm-wave LNA circuits in state-of-the-art CMOS processes.