The proposed time-domain comparator is illustrated in Fig. 2, which is composed of delay cells, two NAND gates, two D-flip-flop register based phase detector and a counter. The operation principle is based on the edge pursuing of two edges originating from two NAND gates similar to [18]. Two flip-flop based register based phase detectors are employed here to judge the polarity of the input. The counter is used to obtain the amount information of the input, which will be used to indicate whether the input is in the predefined window.

Fig. 3 shows the operation principle of the comparator. When RST signal is logic low, the comparator is in reset state. Once RST changes from logic low to logic high, two propagating edges are injected into the oscillator, and travel though the delay cells. The oscillation will stop when one edge overtakes the other one. Fig. 3 illustrates the cases when Vip is larger than Vin but with different amounts. When the voltage difference is small, the two propagating edges have a similar travel speed, and the cycles needed to arrive a decision automatically increase as Fig. 3 shows. On the other hand, if the voltage difference is large, the oscillation will stop very quickly, which inherently reduce the dynamic power consumption. In both cases, outp will settle to 1 (outn will settle to 0 in these cases), which indicates Vip is larger than Vin. Moreover, the oscillation cycles, which is recorded by the counter, can be further utilized to detect the input voltage difference, which facilitates the SAR control logic to improve the whole energy-efficiency of the SAR ADC.

The noise root mean square (rms) level σv of the input-referred voltage and the input-referred offset voltage VOS_N of the comparator can be expressed as [18]:

(1) σv=π3 f0kTI(2VOV(γN+γP)+2VDD)VOV,

(2) VOS_N=1N⋅VOS,

where f0 is the oscillation frequency, k is the is the Boltzmann constant, T is the absolute temperature, I is the current-limiting current, VOV is the overdrive voltage of the current-limiting transistors, VDD is the power supply, VOS is the input-referred offset voltage for one delay cell, γN and γP is the body-effect coefficients of NMOS and PMOS transistors respectively, and N is the number of the delay cell. From Eq. (1), the input-referred noise of the comparator is proportional to f0/I, which is inversely proportional to the capacitor load of the oscillator. Thus, the input-referred noise can be easily tuned by adjust the MOS transistor size or the stages of the delay cell.

Fig. 4 illustrates the working principle window of the skipping-window. When the SAR ADC powers on, the top plates and the bottom plates of the DAC array are all connected to V_cm. Then the control logic changes the connections of the bottom plates in order to generate the window voltage V_win. After the DAC settles, the comparator starts to work and the counter number N_win under V_win will be recorded. N_win will be utilized to indicate whether the input voltage falls into the skipping window during the SAR conversion. A SAR conversion will start after the V_win is set. After the sampling process, the SAR control logic set the current conversion cycle i = 1 and the time-domain comparator compares the DAC output voltages. If the voltage difference is larger than the window voltage V_win, the SAR control logic will perform the normal SAR conversion cycle by cycle; otherwise, the control logic will judge whether the current conversion cycle i is less than the skipping window cycle P_win; if i < P_win, the control logic sets i = P_win, and perform the rest conversion cycles. Once i >= P_win, the control logic will perform the normal conversion.

Fig. 5 shows the conversion process of a 10-bit SAR ADC model with V_win = 64 LSBs. The most significant bit (MSB) cycle is denoted as phase 9, and the least significant bit (LSB) cycle is phase 0. Fig. 5a is a normal conversion process and Fig. 5b is a skipping window conversion process. In Fig. 5a, the input voltage difference is larger than V_win at phase 6, where phase 6 corresponds to the window of 64 LSBs. Thus, no window is skipped for this case. In Fig. 5b, the input falls into the window V_win at phase 8, the next conversion cycle will skip to phase 5 directly, and two comparison cycles are saved. Thus, when the skipping window triggers, the conversion cycles will reduce, which in turn helps to improve the energy efficiency of the SAR ADC as well as the conversion speed and linearity.

The DAC switching scheme employed here is similar to that used in [14]. No additional switch or capacitor is needed. The skipping window technique is realized by the control logic according to the information provided by the comparator. Fig. 6 gives an example of the proposed skipping size with a window size of 64 LSBs. During the sampling phase, the input is connected to the top plates, and the bottom plates of the DAC array are all connected to the common-mode voltage V_cm, which is represented by ‘1/2’ in Fig. 6. Once the sampling phase is finished, the sampling switches are turned off and the first comparison cycle is carried out directly. According to the comparison results, the control logic judges whether the input difference is less than V_win. If |V_ip − V_in| < V_win, it means the input voltage is within the voltage window. Under this case, the skipping step is triggered. If V_ip > V_in, the bottom plates of C5 in the DACp and DACn are connected to ‘0’ and ‘1’, respectively, where ‘0’ represents GND and ‘1’ stands for VDD, and three phases are skipped. If V_ip < V_in, the switching procedure is just opposite to that of V_ip > V_in as the branch B shows in Fig. 6. However, if |V_ip − V_in| > V_win, the skipping procedure is not triggered, and normal conversion process is performed as branches C and D show. It should be noted that, whenever the input voltage is less than V_win before phase 6, the skipping procedure will be triggered, which is different from the incremental algorithm in [17].

To prove the efficiency of the proposed skipping window technique when the input falls in the predefined window voltage V_win, different window voltages are defined to verify the conversion cycle saving. During simulations, a 10-bit SAR ADC model is used. Fig. 7 shows the impact of skipping window size on the percentage of the triggered input. For normal SAR conversion with no skipping window size, all the input will carry out the full conversion cycles, and percentage of the triggered input is 0. When the skipping window size is set to 256 LSBs, the percentage of a full scale input fallen into the skipping window comes to 50%, which can improve the overall energy efficiency of the SAR ADC significantly. When the skipping window size is reduced to 2 LSBs, the percentage is improved to about 99.61%.

As described in Section 2.2, a large voltage range of the full scale input can fall in the skipping window zone if V_win is small. However, when V_win is small, the first MSB cycles can be skipped is less, which results in less energy efficiency of DAC. In order to evaluate the effect of the skipping window size on the DAC switching energy, a 10-bit SAR ADC model with the merged capacitor switching (MCS) scheme in [14] is employed. Fig. 8 shows the DAC switching energy under different skipping window size. It is clearly that when the skipping window size is large, the DAC consumes less switching energy than those with small skipping window sizes. This is because when the window size is large, most MSB cycles can be skipped. As the first few MSB conversion cycles occupies a large amount of the overall DAC switching energy, when the window size is large, the probability of the first few MSB conversion cycles will be skipped is high.

In SAR ADC, most of the power is consumed by three main building blocks, including comparator, DAC capacitor arrays and control logic. Since the DAC switching energy is not the same for different cycles during a conversion, the energy saving with different window size can be evaluated by supposing that each output code has the same probability, and the average DAC switching energy is denoted as E_DAC. For simplicity, we assume that the power consumption for the comparator E_comp and the control logic E_dig do not change for each bit-cycle.

For a normal conversion cycle, the power consumption for the comparator and the control logic are n⋅Ecomp and n⋅Edig for a n-bit SAR ADC, respectively. Assuming that the k-th cycle corresponds to the skipping window, and the corresponding size can be expressed as 2n−k LSBs. According to the skipping window working principle in Section 2.3, if the current conversion cycle i is less than k and the input voltage is small than the window voltage V_win, the cycles between i and k will be skipped. In this circumstance, the power consumed by comparator and control logic can be expressed as

(3) Ecomp,win=(n−k+i)⋅Ecomp

(4) Edig,win=(n−k+i)⋅Edig

where Ecomp,win and Edig,win are the total power consumption of comparator and the control logic respectively when the skipping step is triggered. For the DAC power consumption, it is very complex to give an exact equation, and the simulation is used to evaluate the power saving of the skipping window as Fig. 8 shows. Fig. 9 shows the bit-cycles against output code under different window size for a 10-bit SAR ADC. The bit-cycle saving increases when the window size decreases, which can save the power consumption of the comparator and the control logic of the conversion cycle and accelerate the conversion speed. However, the DAC energy efficiency will reduce with the decreased window.