In CMOS realization RCA [1] offers better structural regularity due to the series arrangement of FA cells. An n bit RCA is constructed using n FA cells cascaded together, with the carryout bit of one FA tied to the carry-in bit of the next higher weight FA cell. However, RCA incurs high carry propagation delay due to rippling of carry signal from least significant bit position to the most. Critical delay of n-bit RCA (t_RCA) is given by (3).

(3) tRCA=n(tFA)

tFA=1(AND)+2(OR)+2(NOT)

where t_FA is the carry generation delay of 1 bit FA cell. From (3), it is evident that the delay of n bit RCA depends on t_FA and it increases in O (n). Hence, minimizing t_FA of 1bit FA cell will minimize t_RCA. From Fig. 1, GC of n-bit RCA is given by

(4) GCRCA=n{7(AND)+4(OR)+10(NOT)}

CSLA [1] performs high-speed addition using an array of RCA pair and 2:1 Muxes. Each RCA block performs addition independently with carry-in as either logic low or logic high. For n = 16, with 4 bits in an RCA block, the CSLA design will have 4 RCA pairs. MUX units use the Carryout (C_out) signal from preceding blocks to produce final output from Sum signals generated by the RCA pair at the corresponding binary weight. Fig. 2 shows the block level architecture for n bit CSLA.

If the carry propagation time of 1bit FA and propagation delay of Mux units are represented as t_FA and t_mux respectively, then delay of n bit CSLA design with m Fas in a block is given by (5)

tCSLA=m(tFA)+nm(tmux)

(5) tCSLA={(m+nm)AND}+{(2m+nm)OR}+{(2m+3n/m)NOT}

From Fig. 2, the gate count of n-bit CSLA is given by

(6) GCCSLA={(9n+2nm)AND}+{(5n+nm)OR}+{(3n+3nm)NOT}

CLA [5,6] eliminates the carry-rippling problem encountered in RCA by generating carry signals at corresponding binary weights using C_in and Propagate (P), Generate (G) signals generated at lower weights. Hence the area cost and hardware complexity of CLA are high for large input bit widths compared to RCA. Following are the functional symbols used to express logic functions viz., |−OR; ∗−AND; ∩−XOR. Based on the above representation, the logic expression for Carry signal (Ci) is given by

(7) Ci=gi−1|[[|j=1i−1gj−1][&k=ji=1pk]|Cin(&l=0i−1pl)]

where, Pi=ai∧bi and Gi=ai&bi and ‘i’ represents the bit position.

Using (7), critical delay of n-bit CLA (t_CLA) is given by

(8) tCLA=(n+1)AND+2(OR)+3(NOT)

Based on AOI representation in Fig. 1, GC of n-bit CLA is given by

(9) GCCLA=7n(AND)+3n(OR)+12n(NOT)

Tab. 1 compares the logic depth and area of the various adders discussed in subsections Figs. 2a–2c, assuming delay and area of each gate to be 1 unit. Note from Tab. 1, RCA performs better in terms of area saving while CSLA performs better in speed improvement. CLA can optimize area and delay significantly.

However, CLA exhibits high hardware complexity and insufficient regularity of cell arrangement compared to RCA for large n, making it unsuitable for CMOS realization. Limiting the number of bits in CLA improves the regularity of structure and reduces hardware complexity. Hence, in the proposed approach input bits are grouped into four, and PC logic-based addition is performed within the group in the accurate part. Furthermore, the approximate part of the adder is implemented with simple OR logic to reduce area and delay.

Error metrics are the essential parameters to evaluate the efficiency of an approximate design in error-tolerant applications. In this section, performance of the proposed approximate adders and state-of-the-art approximate designs is evaluated in terms of various error metrics [19,20] using standard output as the reference. The accuracy metrics considered are: Mean Error Distance (MED), Mean Relative Error Distance (MRED), Normalized Error Distance (NED) and Percentage Accuracy defined as follows.

(19) MED=122N(∑i=122N|EDi|)

(20) MRED=122N(∑i=122NEDiSi)

(21) NED=122N(∑i=122NEDiD)

(22) Percentage of Accuracy(ACC)=[(1−EDRe)×100]

where, ED_i-Error Distance at output combination corresponding to i^th input combination, S_i-exact output corresponding to i^th combination, D-maximum possible ED of an approximate circuit and R_e-exact result.

Tab. 2 compares MED, MRED and NED value of the proposed and prior adder designs. Note from Tab. 2, that proposed adders fares better MED and MRED values compared to ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] designs. AEPA-EFA [19] design use exact full adder cell in approximate and accurate part. Hence MED, MRED and NED values of AEPA-EFA [19] design are significantly better compared to proposed and state-of the art adder designs. P-PCER design fare better in MED, MRED and NED values compared to the P-PC design, thanks to the error recovery unit used in P-PCER design.

Performance of the proposed and state-of the art adders in terms of total power dissipation (power), area, delay, Area-Delay Product (ADP), Power-Delay Product (PDP) and Energy-Delay Product (EDP) are shown in Tab. 3. Note from Tab. 3, P-PC and P-PCER adders demonstrates 30.8% & 28.8%; 35.9% & 34%; 54.7% & 53.4%; 45.5% & 43.8%; 44.7% & 43.1%; 40.3% & 38.5%;58.8% & 57.6%;47.2% & 45.6% and 42.1% & 40.4% power reductions compared to conventional CLA [1], ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] designs respectively. Though SARA [18] implement look ahead based carry propagation in the accurate part, it shows 11.2% and 9.8% high delay compared to P-PC and P-PCER adders, thanks to the parallel carry generation logic that reduce delay of the proposed designs significantly. ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] adders use carry select algorithm and hence delay of these adders depends on the number of FA cells in a block and increases in the order of number of blocks and 2:1 Mux delay. In terms of PDP, P-PC and P-PCER adders demonstrates 50.8% & 48.5%; 35.7% & 32%; 57.3% & 55.3%; 49.3% & 46.9%; 48.9% & 46.6%; 47% & 44.5%; 68.1% & 66.6%; 49.5% & 47.2% and 44.2% & 41.7% reductions compared to conventional CLA [1], ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17],SARA [18], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] adders respectively.

Also note from Tab. 3, P-PC and P-PCER adders show 34.5% & 32.4%; 41.1% & 39.2%; 58.3% & 56.8%; 47.4% & 45.9%; 48.2% & 46.5%; 20.8% & 18.3%; 50% & 48.4%; 45.4% & 43.7% and 41.3% & 39.5% area reductions compared to conventional CLA [1], ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] adders respectively. AEPA-EFA [19] shows the highest area compared to other approximate adders related. On the other hand, AEPA-EFA [19] demonstrates the least error.

Furthermore, it is noted that ADP and EDP metrics of proposed adders are significantly better compared to other approximate adders considered for evaluation. Tab. 4 gives a brief comparison of power, delay, area, PDP and EDP metrics of proposed adders for various bit-widths in input operands (n = 8, 16, 32). It is noted from Tab. 4, area, power and PDP increase at the least by 1.8X, 1.8X and 3X proportion for 2X increase in input operand bit-width. Also, it is noted, the proportion of PDP rise of proposed adders is more for higher bit-widths in input operands.

Fig. 6a shows the efficacy of proposed and other approximate adders in optimizing area and error through area vs. MRED plot, Figs. 6b and 6c exhibits the capability of proposed adders in optimizing ADP, PDP against error through N_ADP-MRED product and N_PDP-MRED product plots. N_ADP and N_PDP, defined as normalized ADP and PDP metrics, respectively, are calculated using (23) & (24).

(23) NADP=ADP of approximate systemADPmax

(24) NPDP=PDP of approximate systemPDPmax

where, ADP_max and PDP_max represent maximum ADP and PDP values of approximate systems compared.

Note from Figs. 6b and 6c, P-PC and P-PCER adders demonstrate low N_ADP-MRED and N_PDP-MRED products compared to ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] adders. AEPA-EFA [19] design shows the least N_ADP-MRED and N_PDP-MRED products compared to the proposed and other approximate adders. Conversely, the area of AEPA-EFA [19] is high, as noted from Fig. 6a. Also, from Fig. 6a, P-PC and P-PCER adders demonstrate the least area and MRED while ET-CSLA [16] demonstrate high MRED and moderate area. SAET-CSLA [16] exhibits high area and moderate MRED, HPETA1 [17] and HPETA2 [17] demonstrates high area and small MRED.

In addition, we have extracted power dissipation of P-PC and P-PCER adders against various operating frequency and temperature using transistor level schematics designed in Cadence Virtuoso design environment and simulations using Cadence Spectre. Fig. 7 shows the Power vs. frequency plot of P-PC adder in 90 and 180 nm ASIC PDK technology.

We have used supply voltage = 1 & 1.8 V for simulations with 90 and 180 nm ASIC PDK technology, respectively. Note from Fig. 7, the power dissipation increases linearly for a rise in frequency. Fig. 8 shows the power vs. temperature plots of proposed P-PC and P-PCER adders in 180 nm ASIC PDK. Note from Fig. 8, power dissipation of proposed adders decreases moderately for a rise in temperature in the range 27 to 120°C and exhibits functionality without any degradation.

To assess the performance of proposed P-PC and P-PCER adders in recurring addition, an implementation in Gaussian Filter (GF) is done. The Gaussian-smoothing filter is a 2-D convolution filter used to remove Gaussian noise and smoothen the noisy input image. Statistical noise having Probability Density Function (PDF) equal to that of the normal distribution is known as Gaussian noise. The PDF of Gaussian random variable is given by:

(25) pG(z)=1σ2πe(z−μ)22σ2

where, z = grey level, μ = mean value and σ = standard deviation.

Fig. 9 shows the block-level architecture of GF. 256 × 256 standard images corrupted with Gaussian noise (μ = 0.2 and σ = 0.005) are used as inputs to the GF system implemented with exact and various approximate adders. Processed outputs of various GFs are shown in Fig. 10.

The quality metrics Mean Square Error (MSE) and Structural Similarity Index (SSIM) between output images processed by approximate and exact GF systems are used as a measure to evaluate the performance of the proposed approximate designs. MSE is given by (26).

(26) MSE=1ab∑i=0a−1∑j=0b−1[S(i,j)−S′(i,j)]2

where, a, b-size of the image; S (i, j) & S’ (i, j) are the exact and approximate filter outputs. Note that, from Fig. 10, SSIM and MSE values of output images processed by P-PC and P-PCER GFs are better compared to ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] GF systems. AEPA-EFA [19] GF system fare better SSIM and MSE compared to proposed and other approximate GFs. This is due to the exact FA cells used in the approximate logic of AEPA-EFA [19], limiting the maximum error to UBP-n/4.

On the other hand, ADP, PDP values of AEPA-EFA [19] are significantly high compared to all other approximate GFs. Note from Fig. 10, visual quality of processed images by P-PC, and P-PCER GFs are better and analogous with output image processed by standard GF. Output image processed by ET-CSLA [16] based GF exhibit poor visual quality with patches due to high error performance. In addition, we have extracted Average MSE (AMSE) metric using different output images processed by approximate GF systems with various standard input images-Lena, Boat, Cameraman, Bridge and Peppers and shown in Fig. 11. It is noted from Fig. 11, AMSE of P-PCER adder based GF is significantly reduced compared to P-PC and other approximate adder based GFs. AMSE of P-PC adder based GF is better compared to ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] based GFs.

Since GF system involves more than one adder, we have evaluated area, ADP and PDP metrics of the system with proposed and prior approximate adders in ASIC platform using Cadence Encounter with 180 nm PDK Technology and shown in Tab. 5. Note from Tab. 5, GF with P-PC and P-PCER adders fare 34.7% & 32.6%; 40.8% & 38.9%; 54.8% & 53.3%; 46.8% & 45.1%; 47.7% & 46.1%; 20.9% & 18.4%; 49.8% & 48.2%; 45.3% & 43.6% and 41% & 39.1% area reductions compared to conventional CLA [1], ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] based filter systems respectively.

Consistently P-PC and P-PCER GFs demonstrate significant ADP reduction compared to all other approximate GF systems related. The processing speed of P-PC and P-PCER adder based GF systems are significantly improved compared to conventional CLA [1], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] based system, thanks to the proposed parallel carry generation logic that reduces the critical delay of proposed adders. ET-CSLA [16] based GF system demonstrates the best processing speed compared to all other approximate systems. Conversely, the AMSE value of ET-CSLA [16] GF is enormous.

Image blending is the process of adding the corresponding pixel values of two input images of the same size. Pixel intensity values of the input images are scaled such that the pixel value of the resulting image does not exceed the maximum threshold. Fig. 12 shows the block-level architecture for image blending. Input images of size 256 × 256, with pixel intensity values scaled by fractional constant ‘α’ and ‘1 − α’ respectively, are fed to the adder unit. Adder unit sums the scaled images to produce the resultant blended image.

Fig. 13 shows the output images processed by the image blending system implemented with proposed and prior approximate adders. Note from Fig. 13, SSIM and MSE values of output images processed by image blending system implemented with P-PC and P-PCER adders are significantly better compared to output images processed by adders considered for comparison. In addition, we have extracted the AMSE metric of various blending systems using processed images for various combinations of standard input images-Lena, Boat, Cameraman, Bridge and Peppers with α = 0.8, 0.5 & 0.2 and shown in Fig. 14. It is noted from Fig. 14, AMSE values of P-PC and P-PCER adder systems are significantly reduced compared to conventional CLA [1], ET CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] systems.