The need for very high-speed low-power VLSI circuits is raised due to rapid increase in communication system’s transmission speeds [1]. Major two driving forces of this high-speed circuit development are high integration level for providing higher performance with lower cost and provision to implementation with low-power system-on-chip. The CMOS is the popular VLSI technology widely used in recent decades [2]. Although, scaling is used for enhancing CMOS technologies performance in a noticeable manner, applications power and speed requirements cannot be satisfied simultaneously by conventional CMOS circuit. Significant supply noise is generated by conventional CMOS circuits. Sensitive digital and analog circuit’s on-chip integration is hindered by conventional methods. MCML is a logic style, which can satisfy the need of high speed with minimized power consumption when compared with traditional CMOS circuits at these high frequencies [3]. The traditional Emitter Coupled Logic (ECL)’s benefits like common mode noise rejection, di/dt noise minimization, high speed without bipolar transistors requirement can be maintained in MCML. For supply noise, higher immunity is provided by MCML architecture because of its differential structure. Because of its minimized output voltage swing, cross talk is minimized and because of constant current flow in supply rails, noise generation also will be very low. A multiplier is one of the most important building block that is widely used in real-time Digital signal Processing (DSP). Multiplier block should be operated with low power, with minimized layout area while operating at high speed in real-time DSP processing task [4]. Now a days, the multiplier is implemented using both the CMOS [5], MCML logic styles [6] to improve the performance. In the past few decades, most promising research area is reversible logic and in various technologies like optical computing, low power CMOS and nanotechnology, they are used [7]. Garbage outputs count, circuits depth, quantum cost can be reduced by designing reversible logic. The inputs and outputs count are same in these reversible logic circuits. Between output and input vectors, there will be an one to one mapping [8–10]. From inputs, outputs can be computed using this and from outputs, inputs can be recovered uniquely using this. In different digital electronic circuits, to provide proper applications processing, basic units like Memory and registers are made using flip flops. One bit of information can be stored in one flip-flop [11,12]. There are four flip-flop types in basic namely, SR (“set-reset”), T (“toggle”), D~(“data”) and JK. In these flip-flop types, major difference are inputs count they have and how they change state. For each type, there are also different variations that enhance their operations. The most common flip-flop topology is the DFF [13], however the MCML implementation of a DFF suffers from transparency issues that cause it to act like a latch. Different digital circuits like registers, clock circuits, memory are designed using MOS Current Mode Logic circuits. Recent works are designed multiplier [14], flip flop [15,16] and registers using MOS Current Mode Logic circuits. However, it has only traditional logic gates that have issues with information loss. To overcome this problem, the proposed work integrates the reversible logic with MCML which is used for designing multiplier, D flip-flop and registers. The main contribution of the proposed research work is the reduction of area and power using reversible logic in designed circuits. This paper is structured as follows: Section 1 describes the information about Complementary Metal Oxide Semiconductor, MOS Current Mode Logic, multiplier and flip-flops. Then, Section 2 explains the technical details of the proposed Reversible Logic Based MOS Current Mode Logic Implementation. The simulation results are given in Section 3. Finally, Section 4 concludes this paper.

The MCML multiplier, Reversible MCML multiplier, MCML based DFF, Reversible MCML based DFF, MCML based 8-bit register and Reversible MCML based 8-bit register are implemented using Tanner EDA tool at 180 nm technology. The performance is analyzed in terms of static power dissipation, average power, static current and area. The simulation output of Reversible MCML based multiplier and Reversible MCML DFF circuits are shown in Figs. 9 and 10 respectively.

The simulation output of the reversible MCML based register is shown in Fig. 11. Tab. 2 summarizes the evaluation of the results of proposed Reversible MCML approach.

Fig. 12 shows the average power of MCML based multiplier, Reversible MCML based multiplier, MCML based DFF, Reversible MCML based DFF, MCML based 8 bit register and Reversible MCML based 8-bit register. In this proposed work, the reversible logic based circuits achieves minimum average power consumption due to its capability to retrieve the input data from output. The proposed reversible MCML multiplier attains 0.683 mW whereas MCML based multiplier achieves 6.19 mW. Average power of the Reversible MCML based DFF is 0.56μW when MCML based DFF attains 5.31 μW. The Reversible MCML based 8-bit register attains 04.04 μW whereas MCML based 8-bit register 8.29 μW.

In Fig. 13, MCML based multiplier, Reversible MCML based multiplier, MCML based DFF, Reversible MCML based DFF, MCML based 8-bit register and Reversible MCML based 8-bit register are analyzed with respect to static power dissipation.

The proposed Reversible MCML multiplier attains 97.2 nW of static power dissipation whereas MCML multiplier achieves 183.2 nW. The Reversible MCML based DFF’s static power dissipation is 1.25 μW when MCML based DFF attains 4.89 μW. The Reversible MCML based 8-bit register attains 1.19 μW whereas MCML based 8-bit register provides 11.85 μW.

The static current comparison of the MCML based multiplier, Reversible MCML based multiplier, MCML based DFF, Reversible MCML based DFF, MCML based 8-bit register and Reversible MCML based 8-bit register are shown in Fig. 14. The proposed reversible MCML multiplier attains 54 nA of static current whereas MCML based multiplier achieves101.7 nA. The static current of the Reversible MCML based DFF is 0.69 μA when MCML based DFF attains 2.71 μA. The Reversible MCML based 8-bit register attains 0.66 μA whereas MCML based 8-bit register achieves 6.58 μA. The experimental results show that the proposed reversible MCML achieves minimum static current than conventional MCML.

Area of the MCML based multiplier, Reversible MCML based multiplier, MCML based DFF, Reversible MCML based DFF, MCML based 8-bit register and Reversible MCML based 8-bit register are shown in Fig. 15. In this proposed work, area is reduced due to the function of reversibility. The proposed Reversible MCML has area of 240 whereas MCML multiplier has 458. Area of the Reversible MCML based DFF is 18 whereas MCML based DFF has 22. The Reversible MCML based 8-bit register has 144 whereas MCML based 8-bit register has 178. As shown in experimental results, the proposed reversible MCML achieves minimum area compared with MCML.

In this proposed research work, multiplier based on reversible MCML, reversible MCML based flip-flop and reversible MCML based register circuits are designed to achieve better area and power. The reversible logic is being used very fast because of its ability in designing a highly complex circuit with minimized power dissipation. The proposed circuit is implemented using Tanner EDA tool at 180 nm technology. From simulation outcome, it is be concluded that the area of proposed reversible MCML based multiplier is 240 which is 47.59% lower than MCML based multiplier, reversible MCML based flip-flop achieves 18.18% of area reduction th\-an MCML based DFF and reversible MCML based register attains 19.10% of area reduction than MCML based register. The performance of the MCML multiplier, Reversible MCML multiplier, MCML based DFF, Reversible MCML based DFF, MCML based 8-bit register and Reversible MCML based 8-bit register are evaluated in terms of static current, static power dissipation, average power and area. In future, reversible logic is applied in C-slow processor with FIFO memory. Here, the performance of processors is enhanced by exploiting multithreading technique in single core processors.